diff --git a/compiler/mips/insts.lisp b/compiler/mips/insts.lisp
index 444bc2b90a0754daf53148aa9173ae2eaa858ecf..4233114e8b013645191e08d4581cb756c82cb347 100644
--- a/compiler/mips/insts.lisp
+++ b/compiler/mips/insts.lisp
@@ -7,7 +7,7 @@
 ;;; contact Scott Fahlman (Scott.Fahlman@CS.CMU.EDU).
 ;;; **********************************************************************
 ;;;
-;;; $Header: /Volumes/share2/src/cmucl/cvs2git/cvsroot/src/compiler/mips/insts.lisp,v 1.10 1990/02/26 23:45:28 wlott Exp $
+;;; $Header: /Volumes/share2/src/cmucl/cvs2git/cvsroot/src/compiler/mips/insts.lisp,v 1.11 1990/03/05 21:06:44 wlott Exp $
 ;;; 
 ;;; Assembler instruction definitions for the MIPS R2000.
 ;;;
@@ -444,6 +444,34 @@
 
 
 
+;;; LOAD-ASSEMBLY-ADDRESS and LOAD-ASSEMBLY-VALUE
+;;; 
+;;; This ``instruction'' emits a LUI followed by either an ADDIU, LW, or SW.
+;;; The difference is that we use :assembly fixups.
+;;;
+(def-instruction-format (load-assembly-format 8) (rt symbol)
+  ;; We need to switch the order of the two instructions because the MIPS
+  ;; is little-endian.
+  (op2 :unsigned 6 :instruction-constant)
+  (rt :unsigned 5 :register)
+  (rt :unsigned 5 :register)
+  (filler :unsigned 16 :constant 0)
+  (op1 :unsigned 6 :constant #b001111)
+  (rt :unsigned 5 :register)
+  (rt :unsigned 5 :register)
+  (symbol :unsigned 16 :fixup :assembly))
+
+(def-instruction load-assembly-address load-assembly-format
+  :op2 #b001001)
+
+(def-instruction load-assembly-value load-assembly-format
+  :op2 #b100011)
+
+(def-instruction store-assembly-value load-assembly-format
+  :op2 #b101011)
+
+
+
 ;;; BYTE, SHORT, and WORD instructions.
 ;;;
 ;;; These instructions emit a byte, short, or word in the instruction