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  1. Mar 01, 2010
    • rtoy's avatar
      o Fix issue where some instructions like MOVLPS would print the · 19f4abf4
      rtoy authored
        arguments in reverse order.  (Ported from SBCL).
      o Work around issue where MOVHLPS and MOVLHPS would be disassembled as
        MOVLPS and MOVHPS.  The instruction is still disassembled
        incorrectly, but we at least add a note indicating the actual
        instruction in these cases.
      19f4abf4
  2. Nov 12, 2008
  3. Apr 25, 2008
  4. Sep 11, 2003
  5. Apr 26, 2003
    • toy's avatar
      8ab36a64
    • toy's avatar
      o Set up a wider opcode column width. · 1ea468d1
      toy authored
      o Update print-fp-reg so that *print-case* will print the FP register
        in the right case
      o Add special printers for all of the FP -sti instructions that store
        the result into the specified FP register.  This makes the syntax
        match the Intel syntax.
      o Correct the instruction printer for the FUCOMI instruction.  (I
        think it works, but FUCOMI isn't used anywhere.)
      1ea468d1
  6. Apr 25, 2003
    • toy's avatar
      · 414c3d96
      toy authored
      o Fix up the instruction printers for FRSTOR and FUCOM which used to conflict.
      o Clean up Lisp code a little.
      414c3d96
  7. Apr 15, 2003
  8. Mar 11, 2003
  9. Feb 25, 2003
    • emarsden's avatar
      Add support for hardware cycle counters for Pentium and UltraSPARC. This · fe40afd6
      emarsden authored
      uses the CPUID + RDTSC instructions on Pentium, and reads the %TICK register
      on UltraSPARC. Accessible via the VM::READ-CYCLE-COUNTER VOP that returns
      two (unsigned-byte 32) values, that are the lower and upper components of a
      64-bit cycle count (actually 63 bits for UltraSPARC). Basic support for
      counting the number of CPU cycles has been added to the TIME macro.
      fe40afd6
  10. Sep 19, 2002
  11. Jun 26, 2001
  12. Jun 04, 2001
  13. May 08, 2001
    • pw's avatar
      From Tim Moore: · fef3f29b
      pw authored
      Add more interesting annotations to disassemble output.
      fef3f29b
  14. Apr 21, 2000
  15. Nov 11, 1999
  16. Sep 28, 1999
  17. Feb 24, 1998
  18. Feb 15, 1998
  19. Jan 29, 1998
  20. Dec 03, 1997
  21. Nov 04, 1997
    • dtc's avatar
      Merge in changes to the x86 backend from the gencgc branch, allowing · 725ab9ee
      dtc authored
      common binaries to be run on both:
      
      * The immediate-stack storage class has been removed, this is
      unnecessary as the descriptor-stack SC can be used. It may have once
      been part of some GC stragety to reduce the number of stack slots that
      needed to be noted for a GC.
      
      * The object allocation has been abstracted and cleaned up. This
      should produce slightly faster smaller code with CGC, and can be
      compiled to support inline allocation with GENCGC.  CGC compiled code
      will run under GENCGC, and GENCGC binaries that don't use inline
      allocation will run under CGC.
      
      * A random hash is now placed in the unused symbol object slot (the
      symbol-hash slot). This saves flushing the info cache at each GC, and
      may have other uses for symbol based hash tables. Should help MP
      safety.
      
      * Common set of static symbols used by both CGC and GENCGC.
      
      * Corrections to the stack-ref VOP; now returns lisp objects not
      unsigned numbers. Required some patches to debug-int.
      
      * Inline unsigned/signed byte 32 to bignum allocation enabled.
      
      * Support for the x86 xadd instruction applied to instance slot and
      symbol values - may be handy for some MP code.
      
      * Bump up the FASL file version from 1 to 2.
      725ab9ee
  22. Oct 18, 1997
  23. Sep 29, 1997
  24. Aug 01, 1997
  25. May 11, 1997
  26. Apr 23, 1997
  27. Apr 13, 1997
  28. Mar 26, 1997
  29. Feb 08, 1997
  30. Jan 18, 1997
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